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| Ordering number : ENN6575 Monolithic Linear IC LA9702W DVD Player Front End Processor Overview The LA9702W is an RF signal-processing and servo error signal generation IC for DVD and CD playback. A DVD player can be implemented by combining this IC with a DVD DSP product that includes a digital servo DSP. Package Dimensions unit: mm 3220-SQFP80 [LA9702W] 14.0 12.0 1.25 0.5 1.25 0.135 Functions and Features * RF signal generation (with built-in gain adjustment VGA circuit) * RF peak detection and generation * RF bottom detection and generation (with time constant switching) * Built-in RF equalizer amplifiers (two systems) * FE amplifier (with built-in balance adjustment VCA and offset cancellation pin) * Three-beam TE amplifier (with built-in balance adjustment VCA and offset cancellation pin) * Reflection amplifier * DPD circuit * Tracking hold circuit * Push-pull TE amplifier (with built-in balance adjustment VCA) * Built-in wobble detection bandpass filter * APC circuits (two systems) * Defect detection circuit 60 61 1.25 41 40 14.0 12.0 1.25 0.5 80 1 0.2 21 1.4 Ratings 6.0 0.1 0.5 0.5 20 SANYO: SQFP80 Specifications Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCC max Pd max Topr Tstg Pdmax for 70C (when mounted on a PCB) Conditions Unit V mW C C 500 -25 to +70 -40 to +150 Note: These specifications are subject to change without notice. Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N2001RM (OT) No. 6575 -1/10 1.6max LA9702W Operating Conditions at Ta = 25C Parameter Recommended supply voltage Operating supply voltage Symbol Vcc Vccop Conditions Ratings 5.0 4.5 to 5.5 Unit V V Electrical Characteristics/Operating Characteristics at Ta = 25C, VCC (pins 12, 55, and 66) = 5 V, ground (pins 17, 49, and 74) = 0 V Parameter Current drain Reference voltage 1 Reference voltage 2 RF gain 1 RF gain 2 PH BH RREC1 RREC2 RRECOST FEGAIN1 FEGAIN2 FEOST Symbol ICC PREF SREF RFG1 RFG2 PH BH RREC1 RREC2 ROST FEG1 FEG2 FOST No signal Pin 79, load current: 2 mA Pin 27, load current: 2 mA Input to pins 1 and 2, pin 21 = SREF - 0.75 V Pin 61 = pin 63 = pin 76 = 5 V, pins 40 and 41 Input to pins 1 and 2, pin 21 = REF + 0.75 V Pin 61 = pin 63 = pin 76 = 5 V, pins 40 and 41 Conditions Ratings min 40 2.3 2.3 0.25 18 typ 58 2.5 2.5 3.25 21 max 75 2.7 2.7 6.25 24 Unit mA V V dB dB V V dB dB V dB dB V Pin 7 = pin 8 = pin 9 = 400 mVpp, pin 21 = SREF - 0.75 V SREF + 0.4 Pin 61 = 5 V, pin 63 = pin 76 = 0 V, pin 44 Pin 7 = pin 8 = pin 9 = 400 mVpp, pin 21 = SREF - 0.75 V SREF - 0.08 Pin 57 = pin 59 = pin 61 = 5 V, pin 63 = pin 76 = 0 V, pin 42 Input to pins 3, 4, 5, and 6, pin 18 = SREF - 0.75 V, pin 76 = 5 V, Pin 28 Input to pins 3, 4, 5, and 6, pin 18 = SREF - 0.75 V, pin 76 = 5 V, Pin 28 Pin 3 = pin 4 = pin 5 = pin 6 = PREF, pin 18 = SREF Pin 76 = 5 V, pin 28 Input to pins 3, 4, 5, and 6, pin 18 = SREF - 0.75 V, pin 76 = 5 V, Pin 29 Input to pins 3, 4, 5, and 6, pin 18 = SREF + 0.75 V, pin 76 = 5 V, Pin 29 Pin 3 = pin 4 = pin 5 = pin 6 = PREF, pin 18 = SREF Pin 76 = 5 V, pin 29 Input such that pin 3 = pin 5 and pin 4 = pin 6, pin 18 = SREF, Pin 76 = 5 V, pin 19 = SREF - 1 V, pin 29: GAIN Input such that pin 3 = pin 5 and pin 4 = pin 6, pin 18 = SREF, Pin 76 = 5 V, pin 19 = SREF + 1 V, pin 29: GAIN Input to pin 10 and 11, pin 18 = SREF - 0.75 V, pin 63 = 0 V, Pin 68 = 0 V, pin 36 Input to pin 10 and 11, pin 18 = SREF + 0.75 V, pin 63 = 0 V, pin 68 = 0 V, pin 36 Pin 10 = pin 11 = PREF, pin 18 = SREF, pin 63 = 0 V Pin 68 = 0 V, pin 53 = 5 V, pin 36 Input to pins 10 and 11, pin 18 = SREF, pin 63 = 0 V Pin 68 = 0 V, pin 20 = REF - 1 V, pin 36 GAIN Input to pins 10 and 11, pin 18 = SREF, pin 63 = 0 V Pin 68 = 0 V, pin 20 = REF + 1 V, pin 36 GAIN The difference in the pin 30 voltage between when input with pin 1 = SREF, pin 2 = 5 MHz with 0 phase, pin 3 = 5 MHz with 36 phase, and when input with pin 1 = SREF, pin 2 = 5 MHz with 36 phase, pin 3 = 5 MHz with 0 phase. RL = 6.8 k The difference in the pin 30 voltage between when input with pin 1 = SREF, pin 2 = 5 MHz with 0 phase, pin 4 = 5 MHz with 36 phase, and when input with pin 1 = SREF, pin 2 = 5 MHz with 36 phase, pin 4 = 5 MHz with 0 phase. RL = 6.8 k 4.2 20 SREF - 0.3 13.9 24 SREF - 0.3 SREF + 0.65 SREF + 0.9 SREF - 0.28 9.2 23 SREF - 0.48 14.2 26 SREF SREF + 0.3 17.9 27 21.9 30 SREF SREF + 0.3 FEBAL1 FBAL1 3.7 6.7 9.7 dB FEBAL2 FBAL2 -9.7 -6.7 -3.7 dB TEGAIN1 TEGAIN2 TEOST TEBAL1 TEBAL2 TEG1 TEG2 TOST TBAL1 TBAL2 11.8 26 SREF - 0.3 4 -10 15.8 29 19.8 32 dB dB V dB dB SREF SREF + 0.3 7 -7 10 -4 DPD phase difference Voltage difference 1 PD1 0.25 0.37 0.48 V DPD phase difference Voltage difference 2 PD2 -0.48 -0.37 -0.25 V Continued on next page. No. 6575 -2/10 LA9702W Continued from preceding page. Parameter Symbol Conditions The difference in the pin 30 voltage between when input with pin 1 = SREF, pin 2 = 5 MHz with 0 phase, pin 5 = 5 MHz with 36 phase, and input with pin 1 = SREF, pin 2 = 5 MHz with 36 phase, pin 5 = 5 MHz with 0 phase. RL = 6.8 k The difference in the pin 30 voltage between when input with pin 1 = SREF, pin 2 = 5 MHz with 0 phase, pin 6 = 5 MHz with 36 phase, and input with pin 1 = SREF, pin 2 = 5 MHz with 36 phase, pin 6 = 5 MHz with 0 phase. RL = 6.8 k Pin 1 = SREF, 2 = 3 = 4 = 5 = 5 MHz, RL = 6.8 k Pin 72 = 5 V Pin 72 = 0 V Pin 70 = 5 V Pin 70 = 0 V Ratings min typ max Unit DPD phase difference Voltage difference 3 PD3 0.25 0.37 0.48 V DPD phase difference Voltage difference 4 PD4 -0.48 -0.37 -0.25 V DPD offset APC1 reference voltage APC1 off level APC2 reference voltage APC2 off level DFFTMU DFFTMD BPF1 BPF2 BPF3 DPDOF LDS1 LDD1 LDS2 LDD2 SREF - 0.5 150 4.5 150 4.5 1.8 SREF SREF + 0.5 180 5 180 5 4 100 5.8 500 5 0 -1 200 200 V mV V mV V S S dB dB dB Pin 2 = 80 kHz. The time difference from a pin 2 edge to DEFTMU the rising edge on pin 46. DFFTMD BPF1 BPF2 BPF3 Pin 2 = 80 kHz. The time difference from a pin 2 edge to the falling edge on pin 46. Pin 34 = 210 kHz, pin 32 Pin 34 = 120 kHz, pin 32 Pin 34 = 3500 kHz, pin 32 -1 -20 -20 2 -4 -6.5 No. 6575 -3/10 LA9702W Functional Description 1. RF amplifier * DVD mode The RF signal input as a differential signal to pins 1 and 2 is passed through the RF VCA and is output from pin 65. The signal output from pin 65 is passed through a DVD RF equalizer and is output to later stage ICs from pins 40 and 41. When pin 63 is high, the RF signal does not pass through the customer amplifier. As a result, it is not influenced by the external peripheral circuit connected to pins 78 through 80. The RF VCA gain is controlled by applying a DC voltage to pin 21. This IC provides two RF equalizer systems, and when pin 61 is high the pin 77 equalizer output is selected, and when low, the pin 52 equalizer output is selected. The amount of boost provided by the RF equalizer can be modified with the pin 22 DC voltage. * CD mode Pins 8, 9, and 10 can be set to be the RF input pins by setting pin 76 low. The customer amplifier connected to pins 78 through 80 is enabled by setting pin 63 low, a CD equalizer circuit can be constructed on pins 78 through 80, and the signal will not pass through the DVD RF equalizer. The RF VCA gain is controlled by applying a DC voltage to pin 21. 2. Peak hold/bottom hold The envelope waveforms for the peak and bottom of the front end RF signal output from pins 40 and 41 are output from pins 42 and 43. The envelope detection constants are set by the values of the resistors inserted between pins 43 and 39 and ground. The bottom hold detection constant can be increased by about a factor of 4 by setting pin 59 low. The bottom hold band width is also be increased by about a factor of 2 by setting pin 57 low. 3. Defect detection The RF signal input from the pickup is converted to binary by a limiter circuit. The binary signal time is observed with a monostable multivibrator, and if there is no change in binary signal for over a certain fixed period, pin 46 is set high. The time period of the monostable multivibrator is set by the value of the capacitor connected to pin 47 and the resistor connected to pin 48. 4. RF equalizer The CD RF equalizer is constructed from external components and the customer amplifier on pins 78 and 80, and outputs to the RF VCA in the next stage. This IC provides two DVD RF equalizer systems, one of which is formed from external components and pins 67, 69, 71, 73, 75, and 77, and the other system is formed from external components and pins 52, 54, 56, 58, 60, and 62. When pin 61 is high, the equalizer system on pins 67, 69, 71, 73, 75, and 77 is selected, and when that pin is low, the equalizer system on pins 52, 54, 56, 58, 60, and 62 is selected. Since the customer amplifier is excluded from the signal path when pin 63 is high, the CD equalizer does not influence IC operation in DVD mode. 5. BCA Peak envelope detection is applied to the previous stage RF signal output from pins 40 and 41. The result is converted to binary by comparison with the BCA threshold and output from pin 45. The BCA threshold is input from external circuits to pin 25. 6. Reflect amplifier The signals input to pins 3, 4, 5, and 6 or pins 7, 8, and 9 are added with an summing amplifier. The pit component is removed from the input signal with a low-pass filter. The summed signal is passed through a VCA that adjusts the servo gain and output from pin 28. The VCA that adjusts the servo gain is controlled by the DC voltage applied to pin 18. Note that when the pin 76 input is high, pins 3, 4, 5, and 6 are selected, and when low, pins 7, 8, and 9 are selected. No. 6575 -4/10 LA9702W 7. FE amplifier The signal input from either pins 3, 4, 5, and 6 or pins 8 and 9 is first passed through an offset adjustment circuit and is then passed through a balance adjustment VCA. Then either the calculation <(pin 3 + pin 5) - (pin 4 + pin 6)> or No. 6575 -5/10 LA9702W Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin RFN RFP PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 VCC LDD1 LDS1 LDD2 LDS2 GND SGC FEBL TEBL VGA BST FOST TOST BCATH REFI SREF RREC FE TE THC WO ISET WOI WOO TEO TEN CP BHI RFON RFOP BH PHI PH BCA DEF DEFC TC GND LPC CPOF EQO2 TH RF signal - input RF signal + input Pickup signal input Pickup signal input Pickup signal input Pickup signal input Pickup signal input Pickup signal input Pickup signal input Pickup signal input Pickup signal input Power supply (servo signal system) APC 1 output APC 1 monitor voltage input APC 2 output APC 2 monitor voltage input Ground (servo signal system) Servo gain control (RREC, FE, and TE) Focus balance adjustment Tracking balance adjustment RF gain adjustment Equalizer boost adjustment Focus offset adjustment Tracking offset adjustment BCA threshold adjustment Reference voltage setting Servo signal reference voltage output Reflection output Focus error output Tracking error output TE hold time constant setting capacitor connection Wobble output Bandpass filter center frequency setting resistor connection Push-pull signal input Push-pull signal output Three-beam TE gain setting Three-beam TE gain setting Charge pump gain setting resistor and capacitor connection Bottom hold detection constant setting resistor connection RF - output RF + output RF bottom detection output Peak hold detection constant setting resistor connection RF peak detection output BCA output Defect output (High: defect detected) Defect detection capacitor connection Defect detection constant setting resistor connection Ground (DPD system) RF DC servo capacitor connection Charge pump on/off control (High: off) RF equalizer setting Tracking hold (High: hold) Function Continued on next page. No. 6575 -6/10 LA9702W Continued from preceding page. Pin No. 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin EQL2 VCC EQO4 XHTR EQI4 XQBH EQ03 EQSCT EQI3 DPD/TE RFO2 RFO1 VCC EQI1 PP/TE EQO1 LDON2 EQI2 LDON1 EQO2 GND EQL1 RFSCT EQO1 CAO PREF CAN RF equalizer setting Power supply (DPD system) RF equalizer setting Tracking and bottom detection band switching (Low: high band) RF equalizer setting Bottom detection time constant switching (Low: fast) RF equalizer setting Equalizer switching (High: pin 77 selected, low: pin 52 selected) RF equalizer setting DPD/three-beam tracking switching (High: DPD) RF output RF output Power supply (RF system) RF equalizer setting Three-beam/push-pull tracking switching (Low: three-beam) RF equalizer setting APC 2 laser on/off control (High: on) RF equalizer setting APC 1 laser on/off control (High: on) RF equalizer setting Ground (RF system) RF equalizer setting RF input switching (High: RF differential input, PP error) RF equalizer setting Customer amplifier output Reference voltage output (pickup) Customer amplifier input Function Note: The equalizer constants support 1x and 2x speeds. No. 6575-7/10 LA9702W Test Circuit No. 6575-8/10 LA9702W Sample Application Circuit The equalizer constants support normal and 2x speeds. No. 6575-9/10 LA9702W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2001. Specifications and information herein are subject to change without notice. PS No. 6575 -10/10 |
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